Logic Firmware

Schematic and VHDL entry

Functional Simulation

Test Bench Generation

High Speed Design
• 3.2Gbps, 100+MHz clock speeds

Specific Design Implementation examples:
• High-speed UART, custom CPU cores, RACE/RACE++, smartcard interfaces, ASIC emulation, motor control, FIR/SIR interfaces, processor interfaces, custom communication buses, memory interfaces (SDRAM and flash), digital filters

FPGAs used:
• Virtex, Virtex II, Spartan II, Spartan 3, Spartan 3E

CPLDs used:
• XC9500, MAX II